Digitizer API

You can interact with the CAEN digitizer boards using the V1729Client class in zmq_client.py. The V1729Client object is created by passing the ip address and port of the ZMQ server already running. For example:

$ python
>>> from zmq_client import V1729Client
>>> client = V1729Client('example.com',5555)

Reading from and Writing to the Digitizer

You can read from and write to the CAEN boards using the read and write methods of the V1729Client class. A full list of the sub addresses for the V1729 board is in the section List of Board Addresses.

Example

Reading the FPGA version:

>>> hex(client.read(0x8200) & 0xff)
'0x68'

Resetting the board:

>>> client.write(0x0800)

By default, if the value is not specified it defaults to 0.

Setting the posttrig:

>>> posttrig = 65535
>>> client.write(0x1a00,posttrig & 0xff)
>>> client.write(0x1b00,posttrig >> 8)
>>> (client.read(0x1a00) & 0xff) | ((client.read(0x1b00) & 0xff) << 8)
65535

V1729Client API

class zmq_client.V1729Client(ipaddr, port)

get_data(timeout=10.0)

Start an acquisition, wait for trigger, and return data in volts.

read(subaddress)

Read the register at subaddress.

set_trigger_source(channel)

Set which channel to trigger from.

set_trigger_threshold(v)

Set trigger threshold in volts.

set_trigger_type(source, edge, random=False, external=False)

Sets the trigger type. See TRIGGER TYPE in CAEN manual on page 33.

source:

0 - software trigger

1 - trigger on discriminator

2 - external trigger from the TRIG_EXT input

2 - logic “OR” of software trigger and trigger on discriminator.

write(subaddress, value=0)

Write to the register at subaddress.

List of Board Addresses

Subadd (HEX)	GPIB	VME	ACCESS	REG or COM.	NAME	bits	Default@ power_on
08	YES	YES	W	Com	RESET BOARD	NO	-
09	YES	YES	W	Com	LOAD TRIGGER THRESHOLD DAC	NO	-
12	YES	YES	W	Com	RESERVED	NO	-
13	YES	YES	W	Com	RESERVED	NO	-
14	YES	YES	W	Com	RESERVED	NO	-
15	YES	YES	W	Com	RESERVED	NO	-
16	YES	YES	W	Com	RESERVED	NO	-
17	YES	YES	W	Com	START ACQUISITION	NO	-
1C	YES	YES	W	Com	SOFTWARE TRIGGER	NO	-
0A	YES	NO	W/R**	Reg	TRIGGER THRESHOLD DAC LSB (byte->GPIB)	8	0
0B	YES	NO	W/R**	Reg	TRIGGER THRESHOLD DAC MSB (half byte->GPIB)	4	0
0A	NO	YES	W/R	Reg	TRIGGER THRESHOLD DAC (word->VME)	12	0
0C	YES	NO	R	Reg	RAM DATA MSB + LSB -> GPIB	8	-
0D	NO	YES	R	Reg	RAM DATA ->VME	16	-
0E	YES	YES	W/R	Reg	RAM_INT_ADD LSB	8	0
0F	YES	YES	W/R	Reg	RAM_INT_ADD MSB	8	0
10	YES	YES	W/R	Reg	MAT CTRL REGISTER LSB	8	0
11	YES	YES	W/R	Reg	MAT CTRL REGISTER MSB	8	0
18	YES	YES	W/R	Reg	PRETRIG LSB	8	0
19	YES	YES	W/R	Reg	PRETRIG MSB	8	40
1A	YES	YES	W/R	Reg	POSTTRIG LSB	8	64
1B	YES	YES	W/R	Reg	POSTTRIG MSB	8	0
1D	YES	YES	W/R	Reg	TRIGGER TYPE	5	0
1E	YES	YES	W/R	Reg	TRIGGER CHANNEL SOURCE	4	0
20	YES	YES	R	Reg	TRIG_REC	1	-
21	YES	YES	W/R	Reg	FAST READ MODES	2	0
22	YES	YES	W/R	Reg	NB OF COLS TO READ	7	128
23	YES	YES	W/R	Reg	CHANNEL MASKS	4	h0F
24	YES	YES	W/R*	Reg	RESERVED	8	90
30	YES	YES	W/R*	Reg	POST STOP LATENCY	8	4
31	YES	YES	W/R*	Reg	POST LATENCY PRETRIG	8	1
80	YES	YES	W/R	Reg	INTERRUPT	1	0
81	YES	YES	W/R	Reg	FP_FREQUENCY	2	1
82	YES	YES	R	Reg	FPGA VERSION	8	-
83	YES	YES	W/R	Reg	EN_VME_IRQ	1	0
FF	YES	NO	W	Reg	NB OF BYTES TO READ IN BLOCK MODE (GPIB)	24 (3x8)	1